VHDL Design

VHDL Design 

A typical VHDL design consists of 4 sections.

1. Entity (for more information Click HERE  )

Entity defines the interface of a design with its outer environment. In this section input/output ports are defined.

2. Architecture (for more information Click HERE  )

This construct is used to define the functionality of the model.

3. Configuration

Configuration determines how all sub-components are combined to become a design and how blocks are connected together.

4. Package

Package is a construction which groups the declarations in order to use them in different designs.

5. Library (for more information Click HERE  )

Libraries are the folders that contain one or more packages.

library library_name;
library IEEE;

6. STD Library (for more information Click HERE  )

It contains the following packages:

• standard = bit,boolean,integer,real, time
• textio = file operation, dosya işlemleri

It's a built-in library. So it is not necessary to reference it in VHDL designs.