Entity

Entity

Entity defines the interface of a design with its outer environment. It is used to determine the relationship of a model with its interface. This section shows the model's outer border, inputs and outputs. Ports are defined in this construct.

Entity Declaration

entity entity_name is
    (
        Generic declaration;
         Port declaration;
      );
end  entity_name;

Example:

entity CLOCK is
      generic (Upper_level : integer := 3  ;
                       time_bit: time :=2 ns  );        
      Port ( CLK : in  STD_LOGIC;
                 OUT : out  STD_LOGIC);
end CLOCK;

Port Declaration: Input and outputs of the model is declared in this section.

entity entity_name is
     Generic declaration; 
      Port ( port_name: port_signal_type  value;
                 port _name:port_signal_type value);
end entity_name;

Three types of ports can be defined with VHDL.

• in:It is the input port which determines signals come from outside of the model..
• out: It is the input port which determines signals go through outside of the model.
• inout: It is the bidirectional port which can be used as both input or output. Especially used in memory applications. 

Generic Declaration: In this section, some parameters of entity transferred to components. Required information can be entered to the design mode in this way.