STD Library (Standard Library)
It contains the following packages:
- standard = bit,boolean,integer,real, time
- textio = file operation, dosya işlemleri
It's a built-in library. So it is not necessary to reference it in VHDL designs.
Data Types Defined in STD Library (Pre-defined)
Signal input:BIT;
"bit_vector" expression indicates that signal is an array of bits.
Signal output :BIT_VECTOR(6 downto 0);
Signal output :BIT_VECTOR(0 to 6);
2. Boolean
It consists of true and false values.
Signal sys_ready: boolean;
3. Integer
It consists of positive and negative decimal values.
It consists of positive and negative decimal values.
Signal level:intger; --32 bits
Signal level :integer range 0 to 31; --5 bits
4. Natural
It consists of Integer values from 0 to 232.
It consists of Integer values from 0 to 232.
5. Positive
It consists of Integer values from 1 to 232..
It consists of Integer values from 1 to 232..
6. Character
It consists of ASCII characters.
It consists of ASCII characters.
7. Time
It consists of time types (ps=piko second, us:mikro second, ms=mili second, sec=seconds, min=minute, hr=hour)
It consists of time types (ps=piko second, us:mikro second, ms=mili second, sec=seconds, min=minute, hr=hour)
Data Types Defined in IEEE.STD_LOGIC_1164 Package
1.STD_LOGIC type
It consists of nine elements explained below :
‘1’ : Logic 1
‘0’ : Logic 0
‘X’ : Bilinmeyen (unknown)
‘U’ : Uninitialized
‘Z’ : Tri-state (high empedans)
‘H’: Zayıf logic 1 (weak logic high)
‘L’ : Zayıf logic 0 (weak logic low)
‘W : Zayıf bilinmeyen (weak unknown)
‘-‘ : Önemsiz (don’t care)
Signal clk:std_logic;
"std_logic_vector" expression indicates that signal is an array of std_logic types.
Signal ready :std_logic_vector(3 downto 0);
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