Usage of "GENERIC" in VHDL using PISO example

  Generics allow a design entity to be described so that,for each use of that component,its structure and behavior can be changed by generic values.In general they are used to construct parameterized hardware components.Generics can be of any type.
Let us understand the use of "generic" with an example.

--The top module has two instantiations

--a 8 bit PISO(parallel in serial out) register and a 4 bit PISO.

--Without the use of generics these two components need a 

--seperate .vhd  file.

--But I have used "generic" keyword to solve this problem.
entity piso is
    generic ( width : integer := 7 );             --default value is 7
port  (  clk : in std_logic;
            load : in std_logic;
            in1 : in std_logic_vector(width downto 0);
            out1 : out std_logic
      );
end piso;
architecture Behavioral of piso is
signal temp: std_logic_vector (width downto 0) := (others => '0');

begin
process(clk)
begin
if (load = '0') then  -- load the register
temp <= in1;
elsif (clk'event and clk = '1') then
--shift the register elements and output a single bit.
out1 <= temp(width);
temp(width downto 1) <= temp(width-1 downto 0);
end if;
end process;
end Behavioral;

--Now the instantiation of this component in top module is shown below:
entity test is
  ...
  ...
end test;
architecture behavior of test is
component piso
     generic ( width : integer := 7 );
port  (  clk : in std_logic;
            load : in std_logic;
            in1 : in std_logic_vector(width downto 0);
            out1 : out std_logic
      );
end component;
--signal declarations
signal in1 : std_logic_vector(7 downto 0):="10000110";
signal in2 : std_logic_vector(3 downto 0):="1001";
signal load1,load2 : std_logic :='0';
begin
--Note down the next two lines.
--This is how you pass generic parameters to the instantiated components.
piso1 : piso generic map (width => 7) port map(clk,load1,in1,o1);
piso2 : piso generic map (width => 3) port map(clk,load2,in2,o2);
--change the input signals as you want.
end behavior;

     

 "generic map (width => 7)" is used to pass the generic parameter to the component.Thus,without writing any extra code you were able to complete your design.

Note1 :- "GENERIC" is a great asset when you use your design at many places with slight change in the register sizes,input sizes etc.But if the design is very unique then,you need not have generic parameters.
Note2 :- Generic's are synthesizable.