First projects with FPGAs

Making Android Accessories with ioio

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Electronic security code lock system

Keypad Input To An Arduino

VHDL Design

VHDL Design 

A typical VHDL design consists of 4 sections.

1. Entity (for more information Click HERE  )

Entity defines the interface of a design with its outer environment. In this section input/output ports are defined.

2. Architecture (for more information Click HERE  )

This construct is used to define the functionality of the model.

3. Configuration

Configuration determines how all sub-components are combined to become a design and how blocks are connected together.

STD Library (Standard Library)

STD Library (Standard Library)

It contains the following packages:

• standard = bit,boolean,integer,real, time
• textio = file operation, dosya işlemleri

It's a built-in library. So it is not necessary to reference it in VHDL designs.

Data Types Defined in STD Library (Pre-defined)

1. Bit
  It consists of 1 ve 0 elements.

Library

Library

Libraries are the folders that contain one or more packages.

library library_name;
library IEEE;

There are two types of libraries.

1. Source Library

Source library contains:

Architecture

Architecture

This construct is used to define the functionality of the model. In this section, the relations between the ports defined in entity.

Syntax:

architecture  architecture_name  of  entity_name  is
   declarations (signal declarations, component declarations, etc...)
   begin
       architecture_body
end architecture_names  ;

Entity

Entity

Entity defines the interface of a design with its outer environment. It is used to determine the relationship of a model with its interface. This section shows the model's outer border, inputs and outputs. Ports are defined in this construct.

Entity Declaration

entity entity_name is
    (
        Generic declaration;
         Port declaration;
      );
end  entity_name;

Example:

VHDL Inverter and Buffer Code

This tutorial in the VHDL course shows how to create an inverter in VHDL code that will invert the signal on a CPLD pin and connect the inverted signal to an output pin. It also shows how to create a buffer in VHDL that simply connects a signal on an input pin to an output pin of the CPLD.

Examples of how to create inverters and buffers on a single input and output pin as well as an input and output bus are used.

Various elements of the VHDL language are explained during the tutorial as they are used. You will learn the following in this tutorial:

Usage of "GENERIC" in VHDL using PISO example

  Generics allow a design entity to be described so that,for each use of that component,its structure and behavior can be changed by generic values.In general they are used to construct parameterized hardware components.Generics can be of any type.
Let us understand the use of "generic" with an example.

BCD to 7-segement display decoder

Here is a program for BCD to 7-segment display decoder. The module takes 4 bit BCD as input and outputs 7 bit decoded output for driving the display unit.A seven segment display can be used to display decimal digits.They have LED or LCD elements which becomes active when the input is zero.The figure shows how different digits are displayed:

D Flip-Flop with Synchronous Reset,Set and Clock Enable

  As per the request from readers I have decided to post some basic VHDL codes for beginners in VHDL. This is the first one, a basic D Flip-Flop with Synchronous Reset,Set and Clock Enable(posedge clock).The code is self explanatory and I have added few comments for easy understanding.

D Flip-Flop with Asynchronous Clear,Set and Clock Enable

  As per the request from readers I have decided to post some basic VHDL codes for beginners in VHDL. This is the second one in the series, a basic D Flip-Flop with Asynchronous Clear,Set and Clock Enable(negedge clock).The code is self explanatory and I have added few comments for easy understanding.

Using real data types in VHDL

  Apart from the standard types like integer and std_logic_vector's VHDL also offer real data types. But a real data type has a big disadvantage. It is not synthesis-able. It can be used only for simulation purposes. This disadvantage limits its use to a large extend, but there are plenty of projects where we look only for simulation results.

  Before starting the coding part of a VHDL project,one has to decide whether the project to be implemented on a real FPGA or just a computer simulation is required. If it has to be ran on FPGA, then forget about the real package and use only synthesis-able data types like std_logic,integer etc... Otherwise you can reduce the time and complexity of your project by using real data types.

How to write a testbench

 Once you finish writing code for your design,you need to test whether it is working or not.One method of testing your design is by writing a testbench code.Without going much into the details I will give you an example.
 Below is a program for a basic 4 bit counter with reset input :

VHDL FAQs

I have included here some of the basic doubts one may have when they start learning VHDL.I will update this list frequently.

1)If my design works perfectly in simulation level ,then does it mean that it will get synthesized?
      No.Simulation is just a way to test your design.If your design works and gives correct outputs at simulation level then you can go for synthesize. Only a subset of VHDL language can be used in synthesizable code.

2)Is "Real" data type synthesizable?
     No."real" is not synthesizable.You have to write your own customized code for dealing with real types.

Usage of Packages and functions

Packages are the only language mechanism to share objects among different design units. Usually, they are designed to provide standard solutions for specific problems, e.g. data types and corresponding subprograms like type conversion functions for different data types, procedures and functions for signal processing purposes, etc.A package is declared in the following format :

Make a speakers for your laptop

Cell phone detector circuit diagram

Amplifiers 4 channels 11W

Make Electronics

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Arduino Projects To Save The World

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FPGAs - World Class Designs

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Verilog HDL A Guide to Digital Design and Synthesis B

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The Designer's Guide to VHDL

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VHDL Programming by Example

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Download the Arduino Software

The open-source Arduino environment makes it easy to write code and upload it to the i/o board. It runs on Windows, Mac OS X, and Linux. The environment is written in Java and based on Processing, avr-gcc, and other open source software.

By downloading the software from this page, you agree to the specified terms.

This page contains the download links to the latest Arduino integrated development environment (IDE) software, release notes, and additional software not included with the IDE .

My first Arduino project.

After reading several books and testing few basic things with my first Arduino kit I decided to try to realize a simple project: a bar graph made of LEDs controlled by a light sensor. Nothing fancy or very original, but I needed something to start!

This is what I used for this project:

• 1x Arduino Uno
• 1x large 700 tie-points breadboard
• 5x 3mm red LEDs
• 5x 220Ω resistors
• 1x LDR light sensor
• 1x 10kΩ resistor
• 9x jumper wires (male-male)

ARDUINO

Beginners often get confused when they discover the Arduino project. When looking for the Arduino, they hear and read strange names such as Uno, Duemilanove, Diecimila, LilyPad, or Seeduino. The problem is that there is no such thing as “the Arduino.” A couple of years ago the Arduino team designed a microcontroller board and released it under an open source license. You could buy fully assembled boards in a few electronics shops, but people interested in electronics could also download its schematic1 and build it themselves.