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VHDL Design

VHDL Design 

A typical VHDL design consists of 4 sections.

1. Entity (for more information Click HERE  )

Entity defines the interface of a design with its outer environment. In this section input/output ports are defined.

2. Architecture (for more information Click HERE  )

This construct is used to define the functionality of the model.

3. Configuration

Configuration determines how all sub-components are combined to become a design and how blocks are connected together.

STD Library (Standard Library)

STD Library (Standard Library)

It contains the following packages:

• standard = bit,boolean,integer,real, time
• textio = file operation, dosya işlemleri

It's a built-in library. So it is not necessary to reference it in VHDL designs.

Data Types Defined in STD Library (Pre-defined)

1. Bit
  It consists of 1 ve 0 elements.

Library

Library

Libraries are the folders that contain one or more packages.

library library_name;
library IEEE;

There are two types of libraries.

1. Source Library

Source library contains: